Conventional field-effect transistors are fabricated using a three mask process. A first mask is used to define an area on a semiconductor wafer for each field-effect transistor by etching a material outside of the photoresist covering developed by using the mask and conventional photolithography techniques. the mesa which is developed through this etching defines the active area of each device and insulates a field-effect transistor from its adjacent neighbors. A second mask is then utilized to define the ohmic contacts which become the source and drain electrodes. After etching the metallic layer so as to define these contacts, the photoresist material deposited through use of the second mask must be removed since the photoresist material cannot withstand the high temperatures used to alloy the contacts. These temperatures are usually greater than 200 degrees C. After alloying the contacts a third mask is then used in order to define an area between the source and drain electrodes which will accommodate the gate structure of the field-effect transistor. Since this third mask must be optically aligned with the source and drain electrodes, it is typical to allow a 1 to 2 .mu.m separation between the gate structure and the source and drain electrodes. A higher speed field-effect transistor could be realized if an even closer tolerance could be obtained between the gate structure and the source and drain electrodes.